Core Catalog and Configuration
The Libero IDE Project Manager Core Catalog contains an extensive list of commonly use configurable cores, created by Actel and optimized for easy instantiation into your design. Select any core on the catalog user interface and a configuration dialog box opens. You can customize the core according to the core type and the specific needs of the design. Upon generation, a structural netlist in EDIF, VHDL, or Verilog is created. For many cores, you can generate VHDL and Verilog behavioral models for most parameterized functions, for use in simulation.
When using SmartDesign, simply select the core name in the catalog to open the configuration dialog. The core is automatically placed on the SmartDesign canvas, where you can then connect it to other cores.
The Core Catalog supports fast selection, configuration, and creation of simple and complex HDL designs for all Actel FPGAs. You can add fabric IP cores into a SmartFusion design, Analog System Builder and IP cores in a Fusion design, and IP cores such as ARM Cortex-M1 and 8051s cores to embedded system designs. A large library of simple gate-level functions is also included.
Active management of cores is handled within the Libero IDE Repository Manager. Libero IDE displays a message at the bottom of the catalog user interface when a new core or core version is available from the Actel's web repository. Downloading the cores is as easy as clicking the download button. You can also direct the Repository Manager to manage or monitor other user-created repositories.
Catalog User Interface within the Libero IDE Project Manager
Libero Standalone (SA) license holders will have access to the Libero IDE Project Manager, which includes the Core Catalog and SmartDesign. Traditional "Designer only" users can create simple or complex processor- and bus-based sytem-on-chip (SoC) designs using SmartDesign, Actel's rich library of functional cores, and their own HDL modules.
For the HDL designer, the catalog also offers an HDL templates selection, providing an extensive list of predefined and proven HDL functions that can easily be selected and instantiated into the HDL source code.
