Live at Power-Up

Actel live at power-up FPGAs are the only devices that can assist in system start-up tasks, system configuration, and supervision during voltage ramp-up. With an Actel device on your board, there is no need for additional live at power-up circuitry, and the device is ready when you most need it, at power-up.

The time it takes for your FPGA to power up has a significant impact on the complexity of your system design and the total cost of your system. Some applications require short system initialization time and cannot wait for device configuration upon power-up. Actel flash and antifuse FPGAs support Level 0 of the live at power-up (LAPU) classification.

Benefits

• Level 0, best in class, live at power-up (LAPU) support
• Operational before power-up
• Orders of magnitude faster power-on than competitors
• Short system initialization time
• Reduction of system power-up components
• Effective and robust system design
• Reduced total cost of ownership

Total System Cost Reduction

In addition to the system operation benefits, the live at power-up function also contributes to reduce the number of components used on-board, reduce power consumption and total system cost, and increase reliability.

For Level-2 LAPU SRAM-based FPGAs, significant additional circuitry may be needed. In addition to a boot PROM and/or additional system memory for unsecure configuration code, a live at power-up CPLD may be needed for system configuration and supervisory tasks. Clock and reset signal generation is also required upon power-up to help initialize components on board. These issues add complexity and cost to the system design and slow down the development process.

By eliminating the need in additional circuitry, Level 0 LAPU nonvolatile FPGAs help in simplifying design, reducing cost, and contributing to efficient use of resources.

The LAPU Cost Difference - Comparing FPGA Total System Cost